The present invention relates generally to exercising semiconductor devices and, more particularly, to performing test and burn-in on semiconductor devices to identify known good die (KGD) and, more specifically, to exercising semiconductor devices at wafer-level (prior to their being singulated, or xe2x80x9cdicedxe2x80x9d, from the wafer)
Semiconductor devices, from microprocessors to memory chips, are fabricated by performing a long series of process steps such as etching, masking, depositing and the like on a silicon wafer. A typical silicon wafer is in the form of a six inch diameter disc, or larger. Many semiconductor devices, typically identical to one another, are fabricated on a single silicon wafer by placing them in a regular rectangular array. Kerf lines (scribe streets) are disposed between adjacent semiconductor devices or the wafer. Ultimately, the devices are singulated from the wafer by sawing along the scribe streets.
Due to defects in the wafer, or to defects in one or more of the processing steps, certain ones of the semiconductor devices will not function as designed, these defects may show up initially or may not be apparent until the device has been in operation for an extended period of time. Thus it is important to test and electrically exercise the devices for an extended period of time to ascertain which devices are good and which are not good.
Typically, semiconductor devices are exercised (burned-in and tested) only after theft have been singulated (separated) from the wafer and have gone through another long series or xe2x80x9cback-endxe2x80x9d process steps in which they are assembled into their final xe2x80x9cpackagedxe2x80x9d form.
From a xe2x80x9cglobalxe2x80x9d perspective, a typical xe2x80x9cback-endxe2x80x9d process flow of the prior art is as follows (commencing with wafer fab):
Wafer Sort #1;
Laser Repair;
Wafer Sort #2;
Wafer Saw;
Package Assembly steps, such as die attach, wire bond, encapsulation, lead trim and form, lead plating;
Electrical Test;
Burn-In;
Electrical Test; and
Mark and Ship product.
Modern semiconductor devices often contain hundreds of terminals (i.e., xe2x80x9cpadsxe2x80x9d such as power, ground, input/output, etc.) and modern semiconductor wafers often contain hundreds of semiconductor devices, resulting in each wafer having tens of thousands of pads, or test points, which need to be accessed in order to carry out testing and/or burn-in at wafer-level (i.e., testing all the dice at one time) prior to singulating the dice from the wafer. Precise alignment is also a non-trivial issue, when dealing with spacings (pitch) between adjacent pads as close as 4 mils. Nevertheless, performing testing and/or burn-in on semiconductor devices, prior to their being singulated from the wafer has been the object of prolonged endeavor.
U.S. Pat. No. 5,570,032 (Atkins, et al.; xe2x80x9cMicron Patentxe2x80x9d; October 1996) discloses wafer scale burn-in apparatus and process wherein a wafer (14) being burned-in is mated to a printed circuit board (13) which electrically contacts the pads on each die on the wafer using small conductive pillars (15) on the printed circuit board. Precise alignment of the entire wafer with the printed circuit board is required in order to permit testing all the dice on the wafer in parallel, eliminating the need to probe each die individually. The apparatus is fitted with heating elements and cooling channels to generate the necessary wafer temperatures for burn-in and testing. The method of utilization eliminates processing of defective dice beyond burn-in and test. FIG. 1 of the Micron Patent provides a general overview of the prior art processing steps in taking a wafer from fabrication to shipment. FIG. 8 of the Micron Patent provides a comparable overview of the processing steps in taking a wafer from fabrication to shipment when utilizing the disclosed method of wafer scale burn-in and testing. It is suggested in the Micron Patent that it is also possible to have a printed circuit board with reduced connections and controlling logic (microprocessors, multiplexers, etc.), and to have complete test electronics included in the printed circuit board (see column 5, lines 53-60).
U.S. Pat. No. 5,532,60 (Tsujide, et al.; xe2x80x9cNEC Patentxe2x80x9d; July 1996) discloses apparatus for testing semiconductor wafer wherein there is a testing substrate, an active circuit disposed on the testing substrate for activating chips disposed on a wafer to be tested, and a plurality of pads disposed on a front surface of the testing substrate and positioned so that the pads are disposed in alignment with bonding pads of the chips disposed on the wafer when the testing substrate is overlaid on the wafer. The testing substrate (2) may be a wafer, made of the same material as the wafer (1) so be tested. On the testing substrate (wafer) 2, lead lines 7 extend from pads 4 and are connected to a power supply, a ground line 8, an I/O line 9, and a chip selecting line 10. FIG. 4 of the NEC PATENT illustrates a testing apparatus 16 made of a silicon wafer, the back surface of which has been etched to have apertures 21 of a quadrangular pyramid shape which can serve as alignment marks to thereby make it easy to register the testing substrate (15) with the wafer (17) to be tested.
U.S. Pat. No. 5,434,513 (Fujii, et al.; xe2x80x9cRohm Patentxe2x80x9d; July 1995) discloses semiconductor wafer testing apparatus using intermediate semiconductor wafer wherein bump electrodes are formed on the bottom surface of an intermediate semiconductor wafer employed as a test substrate, and pickup electrodes and control electrodes are formed on the top (opposite) surface of the test substrate. A switching circuit is formed in the intermediate semiconductor wafer, and serves to connect selected ones of the bump electrodes to the pickup electrodes in accordance with switching control signals provided from a tester via the control electrodes. The pickup electrodes and the control electrodes are connected to the tester via pogo pins.
U.S. Pat. No. 5,497,079 (Yamada, et al.; xe2x80x9cMatsushita Patentxe2x80x9d; March 1996) discloses semiconductor testing apparatus, semiconductor testing circuit chip, and probe card wherein a plurality of semiconductor testing chips (2) are mounted to a one side of a motherboard (4) and a like plurality of on item of semiconductor integrated circuit chips (1) to be tested are mounted to an opposite side of the motherboard (4). A computer (3) is provided for controlling the semiconductor testing chips (2). Since the major testing functions are incorporated into the testing circuit chips (2), the computer (3) for collecting the test results can be a low price computer. FIGS. 5, 7 and 10 of the Matsushita Patent illustrates a representative semiconductor test circuit chip (2) having test pattern generating means, a driver for applying the test pattern to the devices being tested, data storing means, data judging means for judging whether stored output data indicates a failure or not, and means for transferring a judgment result to a work station. FIG. 12 of the Matsushita Patent illustrates the structure of a semiconductor testing apparatus used in a wafer test wherein a plurality of semiconductor testing chips (2) are mounted to a probe card (103), a plurality of probe needles (104) extending from the probe card (presumably from the opposite surface of the probe card), and a wafer (106) being tested. When a control signal is transmitted from the work station to the semiconductor testing circuit chips, the semiconductor testing chips start testing the semiconductor integrated circuits formed on the semiconductor wafer.
Generally, previous attempts at implementing schemes for wafer-level testing have involved providing a single test substrate with a plurality of contact elements for contacting corresponding pads on the wafer being tested. As mentioned hereinabove, this may require many tens of thousands of such contact elements and extremely complex interconnection substrates. As an example, an 8xe2x80x3 wafer may contain 500 16 Mb DRAMs, each having 60 bond pads, for a total of 30,000 connections. There are 30,000 connections to the wafer under test (WUT), 30,000 additional connections to the intermediate substrate, 30,000 more connections to the test electronics, and an undetermined number of connections to the control electronics. Moreover, the fine pitch requirements of modern semiconductor devices require extremely high tolerances to be maintained when bringing the test substrate together with the wafer being tested.
An object of the present invention is to provide an improved technique for performing wafer level burn-in and test.
An object of the present invention is to reduce the cost of manufacturing semiconductors by enabling a series of wafer level processing steps that results in a finished device that has superior physical qualities and higher reliability levels than the prior art will allow.
According to the invention, semiconductor devices are exercised at wafer-level, prior to their being singulated from the silicon wafer upon which they are fabricated. As used herein, the term xe2x80x9cexercisexe2x80x9d includes, but is not limited to, performing burn-in and functional tests on semiconductor devices. A plurality of pressure connections are made between a plurality of unsingulated semiconductor devices under test (DUTs) on a wafer under test (WUT) and a test substrate using interconnection elements such as spring contact elements to effect pressure connections therebetween. The spring contact elements are preferably mounted by their bases directly to the WUT (i.e., to the DUTs on the WUT) so as to have free ends extending to a common plane above the surface of the WUT. The test substrate preferably has a coefficient of thermal expansion which is well-matched with that of the WUT. Alternatively, the spring contact elements are mounted to the test substrate.
According to an aspect of the invention, the spring contact elements are arranged on the WUT so as to fan out, or to have a greater pitch at their tips than at their bases. The spring contact elements are suitably composite interconnection elements such as have been described in the PARENT CASE.
In an embodiment of the invention, the test substrate comprises a relatively large interconnection substrate and a plurality of relatively small substrates mounted and connected to the interconnection substrate, each small substrate being smaller in size (area) than the size (area) of a one of the DUTs. The small substrates are disposed on the front (facing the WUT) surface of the interconnection (support) substrate. It is also possible that one small substrate is bigger than an individual DUT and xe2x80x9cmatesxe2x80x9d with two or more DUTs. The small substrates are suitably active semiconductor devices, such as application-specific integrated circuits (ASICs). The design of the ASIC is such that it enables the number of signals being provided to the test substrate from an outside source (e.g., a host controller) to be minimized.
In the case of spring contact elements mounted to the DUTs, the tips of the spring contact elements are preferably fanned-out so as to be at a greater spacing than their mounted bases, and the ASICs are provided with capture pads (terminals) which may be oversized so as to relax alignment tolerances. The tips of the spring contact elements may fan out, yet be disposed in an area which is still less than and within the area of the DUT to which they are mounted. The ASIC for exercising the DUT is of a size which corresponds to the area of the tips of the spring contact elements.
In an embodiment of the invention, the ASICs are provided with indentations on their front surface, each indentation receiving a tip of a corresponding spring contact element mounted to a DUT. These indentations may be formed directly in the surface of the ASIC, or may be provided by a layer disposed over the surface of the ASIC. After receiving the tips, the ASICs can be moved laterally, or rotated (in-plane), to engage the tips of the spring contact elements with sidewalls of the indentation features.
According to an aspect of the invention, means are provided for ensuring precise alignment of the plurality of ASICs to the interconnection (support) substrate, including indentations on the back surfaces of the ASICs and corresponding indentations on the front surface of the interconnection substrate, and spheres disposed between the ASICs and the interconnection substrate.
According to an aspect of the invention, the test substrate is maintained at a temperature which is lower than the temperature of the WUT. This enables the DUTs on the WUT to be raised to a higher temperature for purpose of accelerating their burn-in, without adversely impacting the life expectancy of the ASICs mounted to the interconnect on substrate. With the coefficients of thermal expansion of the test substrate closely matching that of the WUT, this will result in an insignificant lesser amount of thermal expansion of the test substrate than the WUT. A significant temperature differential between the WUT and the test substrate is readily preserved by disposing the entire apparatus (WUT and test substrate) in a vacuum environment.
In use, the test substrate is placed into contact with the WUT at room temperature. The capture features (e.g., indentations) on the front surface of the ASICs hold the spring contact elements in place. The DUTs can then be powered up. The vacuum environment prevents heat from the powered up DUTs from heating up the ASICs, thereby permitting the ASICs to be operated at a much lower temperature than the burn-in temperature of the DUTs.
According to an aspect of the invention, signals for testing the DUTs are provided by an outside source (host controller) to the plurality of ASICs in a first format such as a serial stream of data over relatively few lines, and are converted to a second format such as a individual signals for the individual relatively many ones of the spring contact elements contacting the DUTs. Alternatively, at least a portion of the signals for testing the DUTs can be generated within the ASICs, rather than supplied by an external host controller.
According to an aspect of the invention, the ASICs can accumulate (monitor) test results from the DUTs, for subsequent transmission to the host controller. This information (test results) can be used to characterize each of the DUTs on an individual basis. Additionally, based on test results from the DUTs, the ASICs can terminate further testing and/or burn-in on a DUT that has failed a critical test.
In another embodiment of the invention the ASICs are fabricated directly on a silicon wafer, rather than being mounted thereto. Redundancy is provided so that defective ASICs or portions thereof can electrically be replaced with one another.
A benefit of the present invention is that the ASICs can inexpensively be made, each xe2x80x9ctypexe2x80x9d of ASIC being specifically designed to accommodate (mate with) a specific type of DUT.
Conventional burn-in techniques involve placing DUTs in a convection oven to elevate their temperatures. In the context of the present invention, it would generally be undesirable to subject the ASICs to such reseated heat cycles. Rather, according to the invention, the DUT(s) and the ASICs are brought into contact with one another and the DUTs are powered-up to perform burn-in. This results in heat being generated by the DUTs, in most cases sufficient heat to satisfy the requirements of elevating the temperature of the DUTs without any additional heat source.
According to an aspect of the invention, the assembly of DUTs and test substrate (interconnection substrate plus ASICs mounted thereto) are placed in a vacuum environment, and the only heat to which the ASICs are subjected will be small amounts of heat conducted to the ASICs along the spring contact elements effecting the electrical connections between the ASICs and the DUTs. The DUT substrate and the test substrate are in contact with liquid cooled chucks whose fluid goes to different controllers. The DUT substrate is taken to a high temperature, typically higher than can be accommodated with packaged parts and the test substrate is maintained at or below room temperature allowing for greatly enhanced electrical operation of the tester.
An advantage of the invention is that the DUTs are in direct contact with the ASICS, and the interconnection substrate which supports the ASICs can be a very low-density wiring substrate receiving very few signals from a host controller, the ASICs themselves generating the bulk of the great many (e.g., 30,000) signals required to exercise a plurality of DUTs on a WUT.
An advantage of the invention is that DUT operation can be ascertained over a wide temperature range, from well below room temperature to the maximum temperature allowed by the semiconductor process, all without thermally stressing the ASICs.
The present invention provides the enabling technology for a full wafer-level assembly process.
Other objects, features and advantages of the invention will become apparent in light of the following description thereof.